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Design Engineer

  • Profile Created:
  • 3 years ago

Skills

Bash Linux SystemC SystemVerilog UVM Verilog VHDL

Education

Experience

  • Current Company 2015 - Present

    Senior design engineer

    Design and implementation of large-scale ASIC and FPGA designs (VHDL). Test environment design in both SystemVerilog (UVM) and C++/SystemC. Software architecture design & implementation for IP & in-house tools (mainly in C++).

  • KU Leuven – ESAT/COSIC 2009 - 2015

    Research assistant

    PhD research on ecient implementations and algorithms for embedded cryptography. Active involvement in multiple FPGA and embedded microcontroller design projects. Supervision of multiple Master theses and of robotic design projects. Organization of the CHES 2012 conference (500+ attendees).

  • Flemish Engineering Student Union (VTK) 2008 - 2009

    Board member

    Responsible for support and improvement of an IT infrastructure for 2000+ students. Planning and execution of a varied set of extra-curricular activities for the students.

Expertise

C++
SystemC
VHDL
Bash
Linux
SystemVerilog
UVM
 
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